Project / Computer architecture

RISC-V Processor with Multicycle Multiplier

A SystemVerilog RV32I single-cycle processor extended with a multicycle M-extension multiplier/divider co-processor.

RISC-VSystemVerilogVivadoFSM

Overview

The design preserves a simple single-cycle datapath for normal instructions while offloading multiplication and division to a synchronized multicycle unit. Dedicated start, busy, and done handshakes prevent the processor from advancing before a long arithmetic operation has completed.

Implementation

Modules include instruction and data memory, register file, ALU, control and immediate-generation logic, branch handling, multiplexers, program counter, and write-back selection. The multiplier uses Idle, Execution, and Completion states and supports MUL, MULH, MULHSU, MULHU, DIV, DIVU, REM, and REMU.

Design outcome

The multicycle strategy reduces arithmetic hardware cost and avoids extending the critical path of normal instructions, making the processor practical for FPGA-oriented academic work.

Selected diagrams

Top-level RISC-V RTL schematic — Top-level processor datapath

Multicycle multiplier block diagram — Multiplier interface and handshake

Control unit block diagram — Instruction-control logic